Edge placement device
US6236427A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2000 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Jan 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2201/04784
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of an edge placement device is supplied with transition data to generate transitions during a pixel time period corresponding to the transition data. The transition data is supplied by pulse code logic that converts pixel data to the transition data. The embodiment of an edge placement device includes first edge placement logic coupled to taps from a first clock delay chain and second edge placement logic coupled to taps of a second clock phase delay chain. Also included is a phase splitter that generate a first and a second clock phase coupled, respectively, to the first and the second clock delay chain from a clock corresponding to a pixel time period. The first and the second clock phase have rising edges on alternate cycles of the clock. The first and the second edge placement logic each include a plurality of D flip flops. The clock inputs of each of the flip flops in the first and the second edge placement logic are coupled, respectively, to one tap from first or the second clock delay chain. The D inputs of the flip flops of the first and the second placement edge placement logic are coupled, respectively, to a first and a second data phase provided by the puls…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.