Nonvolatile semiconductor memory
US6236609A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2000 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Mar 16, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3477
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A potential generating circuit generates two types of erase verify threshold values EVT1 and EVT2. These values satisfy the relationship of EVT2=EVT1+(OEVT-EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT2, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT1 and is lower than OEVT. The erase verify threshold values EVT1 and EVT2 are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT2. On the other hand, during the normal operation, the erase verify threshold value is set at EVT1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.