Digital PLL circuit
US6236696A · kind A · utility
23Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 1998 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | May 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital PLL circuit includes a sampler which samples a burst data signal depending on N phase clock signals to produce N phase sampled data signals. Based on the N phase sampled data signals, an edge phase detector detects edge information and a duty detector detects duty information signals in synchronization with the reference signal. A selector selects an optimal sampled data signal from the N phase sampled data signals depending on the edge information and the duty information, and a retiming section retimes the sampled data signal selected in synchronization with the reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.