Chip layout for implementing arbitrated high speed switching access of pluralities of I/O data ports to internally cached DRAM banks and the like
US6237130A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1998 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Oct 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel chip layout for a network wherein pluralities of I/O data ports are each connected to transmit/receive SRAM buffer banks operable under arbitration units to access pluralities of internally cached DRAM banks via internal busses to enable switching data connections amongst all data ports through the appropriate buffers, the chip layout having, data ports substantially symmetrically placed with each data port connected to each arbitration unit and each transmit/receive buffer bank, and with each data port enabled to write into any DRAM bank, with the connections being effected such that each data port is substantially symmetric with respect to DRAM bank, arbitration unit and transmit/receive buffer banks and busses; and with timing clocks centrally placed on the chip to minimize clock skew by symmetric clock distribution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.