Direct coupling field effect transistor logic (DCFL) circuit
US6239623A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 18, 1998 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Nov 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0952
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a DCFL circuit, a high-speed operation is conducted in a stable state regardless of its load capacitance. The circuit includes a buffer circuit. Added to the buffer circuit is a pull-up circuit conducting a pull-up operation for a predetermined period of time when an output potential of the circuit changes from a low level to a high level. A first EFET of the pull-up circuit includes a gate electrode connected to an output terminal of a logic stage, a drain electrode coupled with a positive power source, and a source electrode linked with a drain of a second EFET. The second EFET includes a gate electrode connected to a node linked in series to a resistor element. The resistor is coupled with an input terminal. The second EFET includes the drain electrode connected to a source electrode of the first EFET and a source electrode linked with an output terminal. Due to the operation of the pull-up circuit for a fixed period of time, the propagation delay time can be minimized without increasing the steady state current when the output potential changes from a low level to a high level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.