Method, architecture and/or circuitry for controlling the pulse width in a phase and/or frequency detector
US6239632A · kind A · utility
8Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1999 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Sep 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) a first signal and a second signal in response to a pump down signal and (ii) a third signal and a fourth signal in response to (i) a pump up signal. The second circuit may be configured to generate (a) a first control signal in response to (i) the first signal and (ii) the third signal and (b) a second control signal in response to (i) the second signal and (ii) the fourth signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.