Synchronous dynamic random access memory with four-bit data prefetch
US6240047A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2000 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Mar 27, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit for operating synchronously with a system clock signal is designed with a memory array (250, 252, 254, 256) having a plurality of memory cells arranged in rows and columns. Each column decode circuit of a plurality of column decode circuits (502) produces a select signal at a respective column select line (108) in response to a first column address signal. A plurality of sense amplifier circuits (202) is arranged in groups. Each sense amplifier circuit is coupled to a respective column of memory cells. Each sense amplifier circuit includes a select transistor for coupling the sense amplifier to a respective data line (203). A control terminal of each select transistor of a group of sense amplifier circuits is connected to the respective column select line. A data sequence circuit (218) is coupled to receive four data bits from four respective data lines (210, 212, 214, 216) in response to a first cycle of the system clock signal. The data sequence circuit produces four ordered data bits in response to a control signal and a second column address signal. A register circuit (220) is coupled to receive the four ordered data bits. The register circuit produces a sequen…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.