Dynamic allocation of bus master control lines to peripheral devices
US6240476A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 1998 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Aug 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a system bus, peripheral devices, bus control logic having bus control lines for bus master operation, and an allocation control circuit. The allocation control circuit is connected to at least one of the bus control lines and at least two of the peripheral devices. The connected bus control line is coupled to one of the connected peripheral devices by the allocation unit so that the one connected peripheral device can operate as a bus master on the system bus. In a preferred embodiment, the allocation control circuit includes switches that are controlled by the system software. Also provided is a method of allocating bus master control lines to peripheral devices. According to the method, the bus master control lines and the peripheral devices are connected to an allocation unit. It is determined which peripheral devices to connect to which bus master control lines, and the allocation unit is directed to couple each bus master control line to one of the peripheral devices so that the selected peripheral devices can operate as bus masters. In a preferred method, the determination is based on user preferences and/or system-detected peripheral devices, and …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.