System for memory based interrupt queue in a memory of a multiprocessor system
US6240483A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1998 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Aug 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0646
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt mechanism which reduces or eliminates the need for an interrupt status register while at the same time provides suitable information to a host or other processor with respect to the cause and parameters surrounding an interrupt signal. An interrupt queue is maintained in shared memory accessible by both a host and an interrupting agent. The interrupt queue has a capacity or two or more separate interrupt requests, either from a same interrupting agent or from two different interrupting agents. As interrupting agents write to the interrupt queue, an agent current interrupt pointer (ACIP) is incremented to a next position in the interrupt queue. As the host services interrupts, the current host pointer is incremented to clear the serviced interrupt request entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.