Method for forming an interconnection in a semiconductor device
US6242340A · kind A · utility
5Cited by
10References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 29, 1999 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Jul 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an interconnection layer in a semiconductor device is provided that improves the mass productivity and the reliability of the interconnection by forming a sidewall spacer on the sidewalls of a trench that is formed in an insulation film having a low dielectric constant. The sidewall spacer maintains the sidewall profile of the trench during subsequent processing steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.