Semiconductor device and manufacturing method thereof
US6242787A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1996 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Nov 15, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
Abstract
A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.