Delay lock loop circuit, system and method for synchronizing a reference signal with an output signal
US6242955A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1999 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Sep 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and system for synchronizing a reference signal and an output signal produced by an electrical circuit, the electrical circuit comprising an analog portion and a digital portion, is disclosed. The method comprises the steps of utilizing the digital portion to produce a phase-adjusted signal and utilizing the analog portion to produce an output signal in substantially the same phase as the phase-adjusted signal. Through the use of the method and system in accordance with the present invention, the large bi-direction shift register of conventional hybrid DLLs is no longer necessary and high speed DLLs will be capable of providing high resolution deskewed clocks in a shorter amount of time. The use of the present invention also facilitates the coverage of a wider range of clock frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.