Semiconductor memory device and signal line switching circuit
US6243301A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1999 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Nov 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Redundancy function with excellent repair efficiency is implemented by specifying a single address for a semiconductor memory device of a multi-bit accessing type. A memory array includes a plurality of memory segments associated with respective addresses. Each memory segment is coupled to a data bus multiplexer via an associated first data bus. A sub-data bus, which includes a larger number of signal lines than that of those included in the first data bus, is provided for each memory segment. These signal lines are connected to associated bit lines in each memory sub-array. A data bus switching circuit is associated with each memory segment to electrically connect the respective signal lines included in the first data bus to the counterparts included in the sub-data bus to meet a predetermined relationship by cutting one of fuses off. In this manner, redundancy function with excellent repair efficiency is implementable on a bit-by-bit basis, not on an address basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.