Circuit and method for automatically regulating the equalization duration when reading a nonvolatile memory
US6243310A · kind A · utility
2Cited by
3References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 11, 2000 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Apr 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An equalization control circuit having an equalization signal generating stage having an enabling input receiving an address transition signal, a disabling input receiving a disabling signal, and an output generating an equalization control signal. An auxiliary line is supplied at one initial terminal (35a) with a biasing voltage correlated to the reading voltage supplied to the addressed array cell. An equalization filter is connected to the end terminal of the auxiliary line and generates the disabling signal when the voltage at the end terminal of the auxiliary line exceeds a preset threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.