Multistage interconnect network uses a master processor to perform dynamic configuration for all switch nodes based on a predetermined topology
US6243361A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1998 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Nov 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13332
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 .vertline.log.sub.b N.vertline. stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and .vertline.log.sub.b N.vertline. indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.