Packaging enhanced board level opto-electronic interconnects
US6243509A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 2000 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Aug 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/0274
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A planarized signal communications system (110) embedded within a printed circuit board (102) is disclosed, comprising first (118) and second (120) index buffer layers within the printed circuit board, a polymer waveguide (116) disposed below the first and above the second index buffer layers, an electrical-to-optical transmitter (122) disposed within the first index buffer layer in direct adjoinment with the polymer waveguide, a reflective element (126) disposed within the polymer waveguide in direct alignment with the electrical-to-optical transmitter and adapted to reflect optical energy from the electrical-to-optical transmitter along the polymer waveguide, an optical-to-electrical receiver (124) disposed within the first index buffer layer and in direct adjoinment with the polymer waveguide, a reflective element (126) disposed within the polymer waveguide in direct alignment with the optical-to-electrical receiver and adapted to reflect optical energy from within the polymer waveguide to the optical-to-electrical receiver, and an at least partially metal layer (128) within the printed circuit board fabricated to provide electrical coupling between the electrical-to-optical tra…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.