Partitioned shift right logic circuit having rounding support
US6243728A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 12, 1999 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Jul 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49952
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A partitioned shift right logic circuit that is programmable and contains rounding support. The circuit of the present invention accepts a 32-bit value and a shift amount and then performs a right shift operation on the 32-bits and automatically rounds the result(s). Signed or unsigned values can be accepted. The right shift circuit is partitioned so that the 32-bit value can represent: (1) a single 32-bit number; or (2) two 16-bit values. A 1 bit selection input indicates the particular partition format. In operation, if the input value is not negative, then one ("1") is added at the guard bit position and a right shift with truncate is performed. If the input is negative and the guard bit is zero, then no addition is done and a right shift with truncate is performed. If the input is negative and the guard bit is one and the sticky bit is zero, then no addition is done and a right shift with truncate is performed. If the input is negative and the guard bit is one and the sticky bit is one, then one is added at the guard bit position and a right shift with truncate is performed. The shift circuitry used by the present invention is fully partitioned to accept word or half-word input…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.