Correct carry bit generation
US6243733A · kind A · utility
1Cited by
16References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1998 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Sep 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49947
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiply add carry (MAC) circuit correctly determines the value of a carry bit when an operation X*Y+Z is undertaken, where X, Y and Z are real numbers and where an accumulator and rounding are utilized. The circuit (1) determines if the product X*Y is negative, (2) determines if the value in the accumulator is negative, (3) determines if a round bit propagates all the way to the most significant bit (MSB) position, (4) determines if the result X*Y+Accumulator+round is negative; and (5) determines a correct carry bit based on the other determinations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.