Cache architecture to enable accurate cache sensitivity
US6243788A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1998 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Jun 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique of monitoring the cache footprint of relevant threads on a given processor and its associated cache, thus enabling operating systems to perform better cache sensitive scheduling. A function of the footprint of a thread in a cache can be used as an indication of the affinity of that thread to that cache's processor. For instance, the larger the number of cachelines already existing in a cache, the smaller the number of cache misses the thread will experience when scheduled on that processor, and hence the greater the affinity of the thread to that processor. Besides a thread's priority and other system defined parameters, scheduling algorithms can take cache affinity into account when assigning execution of threads to particular processors. This invention describes an apparatus that accurately measures the cache footprint of a thread on a given processor and its associated cache by keeping a state and ownership count of cachelines based on ownership registration and a cache usage as determined by a cache monitoring unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.