Digital data bit order conversion using universal switch matrix comprising rows of bit swapping selector groups
US6243808A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 1999 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Mar 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/768
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method of performing random bit swapping including bit (single bit) swapping, nibble (4-bit) swapping, byte (8-bit) swapping, and half word (16-bit) swapping including a matrix of rows of two-to-one multiplexers. Each row of multiplexers shares the same control signal such that all of the multiplexer in a given row either outputs a "non-swapped" bit value or a "swapped" bit value. In addition, multiplexers are grouped within rows to allow 2-bit, 4-bit, 8-bit, and n-bit swaps in each consecutive row. Depending on the shared multiplexer controls for each row, the matrix can be programmed to perform any swapping function or possible bit pattern. The number of bits output by the matrix determines the number of rows used, e.g., an 8-bit dataword uses 3 rows, 16-bit word uses 4 rows, 2.sup.N -bit word uses N rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.