Method and apparatus for operating on a memory unit via a JTAG port
US6243842A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1998 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Jun 8, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of controlling the operations of an on-chip memory unit includes the steps of receiving an indication of at least the ready or busy state of the memory unit and instructing the memory unit to perform the next operation once the indication is of the ready state. The step of receiving can include the repeated steps of capturing the indication and the data and address information of the previous byte provided to the memory unit and shifting the data and address information of a next byte and at least one extra bit through a shift register such that the indication is also shifted out of the shift register to a data out pin of a JTAG port. The steps of capturing and shifting, which provide double buffering, are repeated until the indication is of the ready state. Alternatively, the step of receiving occurs from a non-JTAG port of the chip to a pin on a receiving port. The present invention includes the chip which can operate according to the steps of the method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.