Top gate self-aligned polysilicon TFT and a method for its production
US6245602A · kind A · utility
24Cited by
6References
6Claims
0Family size
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Key dates
| Filing date | Nov 18, 1999 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Nov 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6723
Abstract
A top gate, self-aligned polysilicon (poly-Si) thin film transistor (TFT) is formed using a single laser anneal to crystallize the active silicon and to activate the source-drain region. The poly-Si TFT includes a substrate, dummy gate, a barrier oxide layer, a polysilicon pattern having a source region and a drain region, a gate oxide, and a gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.