Method for fabricating a semiconductor structure

US6245640A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Wilhelm Claussen · Dresden, DE
• Barbara Lorenz · Dresden, DE
• Klaus Penner · Radeberg, DE
• Mirko Vogt · Dresden, DE
• Hans-Peter Sperlich · Dresden, DE

Key dates

• Filing date: Sep 27, 1999
• Grant date: Jun 12, 2001
• Expiry date: Sep 27, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31111
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An antireflection layer, preferably a dielectric antireflection layer, is applied by PECVD to a hard mask layer which is composed of doped silicon oxide, with no interruption of the vacuum. The silicon oxide layer is then patterned to form a hard mask and, by way of example, a deep trench etching is performed. The hard mask is removed using an HF/H.sub.2 SO.sub.4 mixture or using an HF/ethylene glycol (EG) mixture at a high etching rate. If the HF/EG mixture is used, an intermediate layer that may be disposed underneath can simultaneously be etched back by a predetermined amount. The integration of two wet etching steps constitutes a major simplification compared with the previous wet etching methods in two different installations.