Semiconductor device and method of fabricating the same
US6245665A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 1999 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Dec 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1036
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device equipped with the dual damascene structure that is provided, which suppresses the propagation delay of signals effectively without using any complicated processes. The device is comprised of (i) a semiconductor substrate having a lower wiring layer and electronic elements; (ii) a first interlayer dielectric layer formed on the substrate; (iii) a second interlayer dielectric layer formed on the first interlayer dielectric layer, the second interlayer dielectric layer being made of carbon-containing SiO.sub.2 ; (iv) a third interlayer dielectric layer formed on the second interlayer dielectric layer; (v) a fourth interlayer dielectric layer formed on the third interlayer dielectric layer, the fourth interlayer dielectric layer being made of carbon-containing SiO.sub.2 ; (vi) the first and second interlayer dielectric layers having a via hole penetrating therethrough; (vii) the third interlayer dielectric layer having a recess overlapping with the via hole, the recess being formed to communicate with the via hole; (viii) a metal plug formed in the via hole to be contacted with the lower wiring layer or the electronic elements in the substrate; (ix) a metal wirin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.