Integrated circuit package architecture with improved electrostatic discharge protection
US6246113A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 17, 1998 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Sep 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An IC package architecture with electrostatic discharge (ESD) protection is provided for use on an IC package for the purpose of allowing the ESD robustness of the IC package to be further enhanced and the structural complexity of the same to be further simplified as compared to the prior art. The IC package includes a lead frame having a die pad for mounting an IC chip thereon, a plurality of package pins with some no-connect pins which are grouped into at least one no-connect pin unit, each unit consisting of one single no-connect pin or a number of consecutively arranged no-connect pins. ESD protection can be provided to any no-connect pin unit on the IC package either by arranging a pair of power pins proximate to the respective sides of the no-connect pin unit; by arranging a power pin proximate to one side of the no-connect pin unit and an elongated conductive tongue proximate to the other side; or by arranging a pair of elongated conductive tongues proximate to the respective sides of the no-connect pin unit. This provides ESD protection to all the no-connect pins in the no-connect pin unit without having to connect them to ESD protection circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.