Sidewalls for guiding the via etch
US6246120A · kind A · utility
5Cited by
12References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 1999 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Sep 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76852
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method to direct the via 270 etch to the top of the interconnect 210, by using a sidewall layer 240, preferably. TiN, and thus preventing the etching down the side of the interconnect 210 and exposure of materials residing between the interconnects 210.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.