PMOS low drop-out voltage regulator using non-inverting variable gain stage
US6246221A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 20, 2000 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Sep 20, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A high power supply ripple rejection (PSRR) internally compensated low drop-out voltage regulator using an output PMOS pass device. The voltage regulator uses a non-inversion variable gain amplifier stage to adjust its gain in response to a load current passing through the output PMOS device such that as the load current decreases, the gain increases, wherein a second pole associated with the voltage regulator is pushed above a unity gain frequency associated with the voltage regulator. The non-inversion variable gain amplifier is further operational to adjust its gain in response to a load current passing through the power PMOS device such that as the load current increases, the gain decreases, wherein the voltage regulator unity gain bandwidth associated with the loop formed by the compensation capacitor is kept substantially constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.