Semiconductor memory device
US6246631A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 22, 2000 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Jun 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a semiconductor memory device having an NK refresh cycle, which can lower an enable speed of a word line by reducing a resistance and a capacitance of the word line enabled during an access operation by using a redundant row address. When the 2NK and NK refresh operations are simultaneously embodied, the read/write operation is carried out by using an address compressed in the device set up by the NK refresh operation. As a result, as compared with the 2NK refresh operation, a length of the word line to be enabled is reduced to a half, and the number of the cells connected to the word line is also decreased, thereby remarkably improving the speed at the row path side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.