Method and apparatus for comparing real time operation of object code compatible processors
US6247144A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1994 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Dec 13, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1687
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for comparing the real time operation of two object code compatible processors to discover incompatibilities and provide fault-tolerance in a computer system. The two processors run the same code and compare their write operations in real time. Logic external to the processors arbitrates between them, granting only one processor access to the system bus at any one time. The first processor executes instructions until it reaches a write or I/O data read cycle, at which time control of the system bus passes to the second processor. The second processor executes the instructions previously executed by the first processor until it catches up to the cycle pending on the first processor. If this cycle is a write cycle, then error detection logic compares the signals pending on the two processors to flag inconsistencies. If the cycle is an I/O data read cycle, the data provided to the first processor is latched to guarantee that the second processor receives the same data for its equivalent cycle. The invention includes logic circuitry which accounts for internal differences between the two processors as well as logic which allows the processors to compare their wri…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.