Incremental method for critical area and critical region computation of via blocks
US6247853A · kind A · utility
72Cited by
9References
14Claims
0Family size
Assignee
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Key dates
| Filing date | May 26, 1998 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | May 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An efficient computer implemented method computes critical area for via blocks in Very Large Scale Integrated (VLSI) circuits. The method is incremental and takes advantage of the hierarchy in the design. In order to increase the efficiency further we use the L.sub..infin. or the L.sub.1 metric instead of the Euclidean geometry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.