Method for suppressing parasitic effects in a junction-isolation integrated circuit
US6248616A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2000 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Jan 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
Abstract
A suppression method is applied to an integrated circuit formed on a substrate of p-type material having at least one region of n-type material with junction isolation, a first electrical contact on the frontal surface of the substrate, a second electrical contact on the n-type region and a third electrical contact on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact is taken to the potential of the second contact, otherwise they are held at the (ground) potential of the reference terminal. A device and an integrated circuit which utilize the method are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.