Sequential correlated double sampling technique for CMOS area array sensors
US6248991A · kind A · utility
30Cited by
6References
37Claims
0Family size
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Key dates
| Filing date | Dec 30, 1998 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Dec 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2209/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A CMOS area array sensor with reduced fixed pattern noise. Device threshold voltage variations are minimied using a Sequential Correlated Double Sampling technique in a column circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.