Semiconductor device and fabrication method thereof
US6249015A · kind A · utility
7Cited by
5References
4Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jul 15, 1998 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Jul 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly formed on a thin SiO.sub.2 layer which is formed to cover a side surface of the gate electrode. A contact hole is formed to penetrate an interlayer insulating layer formed on an SiN stopper layer and reach the main surface of the silicon substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.