Device method for enhanced avalanche SOI CMOS

US6249029A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Andres Bryant · South Burlington, US
• William F. Clark, Jr. · South Burlington, US
• John J. Ellis-Monaghan · Grand Isle, US
• Edward P. Maciejewski · Wappingers Falls, US
• Edward J. Nowak · South Burlington, US
• Wilbur D. Pricer · Burlington, US
• Minh H. Tong · Saint Johnsbury Center, US

Key dates

• Filing date: May 26, 1999
• Grant date: Jun 19, 2001
• Expiry date: May 26, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.