Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit
US6249145A · kind A · utility
35Cited by
6References
34Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 11, 1998 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Dec 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.