Synchronous frequency dividing circuit
US6249157A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 1999 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Jul 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/54
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
First to third D flip-flops, fourth to sixth D flip-flops, and a delay circuit are provided. The first to third D flip-flops frequency-divide a clock signal. The fourth to sixth D flip-flops are provided corresponding to the first to third D flip-flops for latching frequency-divided outputs from corresponding D flip-flops and outputting them in synchronization with the clock signal. Accordingly, the frequency-divided outputs from the fourth to sixth D flip-flops are synchronized with the clock signal with a delay of prescribed time. The delay circuit outputs the clock signal after a delay of the prescribed time. Thus, the output of the delay circuit and the frequency-divided outputs are synchronized without delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.