Frequency control circuit having increased control bandwidth at lower device operating speed
US6249159A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 1999 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Dec 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to an embodiment of the invention, an apparatus is disclosed which includes a phasedetector (PD) that is capable of providing a number of first control signals, where each control signal is responsive to a phase error measured at a different time between a first oscillatory signal and one or more second oscillatory signals. The apparatus further includes a capacitor circuit that is coupled to the PD and has a number of charge storage devices. Each charge storage device has a predetermined capacitance. The capacitor circuit is adapted to provide an amount of charge to a filter node in response to a respective one of the first control signals. A voltage of the filter node is filtered and fed to a controllable oscillator. The one or more second oscillatory signals are derived from the output of the oscillator, thus forming a closed loop frequency control circuit. The invention can be applied in a wide range of frequency control circuits, including phase locked loops (PLL), delay locked loops (DLL), and clock and data recovery circuits (CRC).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.