Sigma-delta modulator and method for suppressing a quantization error in a sigma-delta modulator
US6249238A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 23, 1999 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Sep 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/436
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sigma-delta modulator is disclosed for conversion of an analog or digital low frequency signal of high resolution into a quantized analog or digital signal, with an error feedback circuit for suppression of quantization errors. The sigma-delta modulator includes a delay device (Z.sup.-1) for delaying the input signal (X) for a plurality of scanning periods to obtain a plurality of delayed input signals (X.sub.i), wherein i=1, 2, . . . , n and the ith one of the delayed input signals (X.sub.i) is delayed for i scanning periods; an adder (2) for addition of the delayed input signals (X.sub.i) each delayed by the i scanning periods to obtain a first sum signal (S.sub.1); a quantizing device (Q, Q.sub.0, Q.sub.1 to Q.sub.n) for producing quantized input signals (VZ.sub.i) each delayed by the ith scanning period; an adder (3) for addition of the delayed quantized input signals (VZ.sub.i) to obtain a second sum signal (S.sub.2); and a subtraction device (1) for subtraction of the sum signals (S.sub.1, S.sub.2) from an actual value of the input signal (X).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.