Flash memory device with a status read operation
US6249461A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2000 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Jun 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/20
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Is herein disclosed a flash memory device which provides a status read operation for indicating its status of operation. In the flash memory device, a first group of data output circuits are coupled to first data input/output pins each of which outputs a status data signal associated with the status read operation. A second group of data output circuits are coupled to second data input/output pins each of which is reserved during the status read operation. A data output circuit coupled to at least one of the first data input/output pins generates a toggled status data signal so that the toggled status data signal to be outputted via the at least one pin at an Nth cycle of an output enable signal is generated at a (N-1)th cycle of the output enable signal during the status read operation. Each of the second data input/output pins is maintained at a predetermined state(e.g., `1`, `0` or Hi-Z) by a corresponding data input/output circuit during the status read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.