Synchronous memory
US6249482A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2000 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Feb 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous single port random access memory comprises a core 2 of memory cells 3 arranged as rows and columns. The rows are addressed by a row decoder 5 and the memory cell outputs are connected as columns to a column decoder and multiplexer 7. The decoder and multiplexer 7 selects groups of memory cells 3 from the addressed row and connects these to sense amplifiers 8. Changes in address are propagated immediately to the core 2 so that the selected memory cells 3 are connected as quickly as possible and without any fixed delays to the sense amplifiers 8. Similarly, a read clock "rclk" enables the sense amplifiers 8 immediately upon becoming active.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.