Apparatus and method for performing timing recovery
US6249557A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1998 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Mar 3, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A timing recovery circuit is disclosed that prevents phase error over-compensation. The timing recovery circuit includes a phase scanner for determining when phase error over-compensation has occurred and generating a signal for preventing dual phase compensation in response thereto thereby providing an accurate recovered clock signal. The timing recovery circuit also includes a feed-forward equalizer having a plurality of taps providing coefficients for filtering and adapting the input timing recovery circuit to an input signal. The phase scanner compares the tap coefficients to generate signal for preventing phase over-compensation by the feed-forward equalizer. A phase detector is provided for sampling coefficients from the feed-forward equalizer, error signals and output data and generating a phase signal used to generating the recovered clock signal. The signal for preventing phase over-compensation is mixed with the phase signal to generate the recovered clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.