Method for supporting cache control instructions within a coherency granule
US6249845A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1998 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Aug 19, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for improving data processing in an L2 cache for symmetrical multiprocessing systems consists of efficient execution of cache control instructions without having to give up the data bandwidth provided by a greater byte coherency granule. The L2 cache has a coherency granule size within its data array and is divided into a target sector and an alternate sector. Additionally, the coherency granule has a plurality of MESI bits, which define sector write enables, and data write enables. By determining the states of the target sector and/or the alternate sector a series of L2 cache control instructions are performed to signal the L2 cache to hit. If a hit occurs corresponding data will be either written into or read out of the data array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.