Interface circuit using plurality of synchronizers for synchronizing respective control signals over a multi-clock environment
US6249875A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1998 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Sep 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuitry is described for transferring information from a first timing environment to a second timing environment. The circuitry comprises a dual port RAM having a first port which is responsive to a first timing signal and a second port which is responsive to a second timing signal, a first control circuit which is responsive to the first timing signal, for controlling storage of data in the dual port RAM through the first port and for generating a control signal indicating that data is stored in the dual port RAM. The circuitry also comprises a synchronizer for synchronizing the control signal to the second timing signal, and a second control circuit, which is responsive to the second timing signal and the synchronized control signal and is for controlling retrieval of stored data through the second port of the dual port RAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.