Method and apparatus for generating and maintaining electrical modeling data for a deep sub-micron integrated circuit design
US6249903A · kind A · utility
Inventors
Key dates
| Filing date | Mar 31, 1998 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Mar 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parasitic extraction tool (PEX) is provided to generate electrical modeling data for an integrated circuit (IC) design, e.g. a deep sub-micron IC design. The PEX includes a read function for reading extracted connectivity and geometrical data of various layout cell hierarchies of the IC design, that are organized and indexed by layout nets. The PEX also includes a write function for writing generated electrical modeling data into a parasitic database (PDB), which is physically organized to accommodate physical storage of the electrical modeling data in multiple physical media, and concurrent usage of the electrical data by multiple client applications, e.g. post layout analysis tool. In one embodiment, the PDB further includes an application interface that shields the physical organization of the PDB, and a logical abstraction of the physical organization to facilitate implementation of the application interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.