Method to provide low dielectric constant voids between adjacent conducting lines in a semiconductor device
US6251799A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1999 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Jul 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to provide low dielectric constant voids between adjacent conducting lines in a semiconductor device. Narrowly spaced metal lines are formed on the substrate surface. A dielectric layer is deposited overlying the metal lines and the substrate surface. A high water content, water saturated, environment is created for the spin-on-glass process. A pseudo-water condition exists on the surface of the dielectric layer prior to the deposition of the spin-on-glass layer. The spin-on-glass layer is deposited overlying the dielectric layer. Voids form in the spin-on-glass layer between the narrowly spaced metal lines. The spin-on-glass layer is baked. The integrated circuit device is completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.