Self-aligned lateral DMOS with spacer drift region
US6252278A · kind A · utility
50Cited by
6References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 18, 1998 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | May 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/517
Abstract
An LDMOS transistor formed in an N-type substrate. A polysilicon gate is formed atop the N-type substrate. A P-type well is formed in the N-type substrate extending from the source side to under the polysilicon gate. A N+ source region is formed in the P-type well and adjacent to the polysilicon gate. A N+ drain region is formed in the N-type substrate and in the drain side of the polysilicon gate. Finally, an N-type drift region is formed between the N+ drain region and the polysilicon gate, wherein the N-type drift region does not extend to said polysilicon gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.