LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device
US6252419A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 1999 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Aug 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An LVDS interface for a programmable logic device uses phase-locked loop ("PLL") circuits to provide data clocks for data input and output. The PLL clocks are highly accurate and each includes a multiply-by-W counter so that a multiplied and an unmultiplied clock are available. The multiplied clock is used to clock data into or out of a shift register chain serially. The unmultiplied clock is used to load or read the registers in the shift register chain in parallel. Providing both the multiplied and unmultiplied clocks from a single PLL assures that the clocks are in proper phase relationship so that the serial inputting or outputting, and the parallel loading or unloading, are properly synchronized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.