Compensation process for a disturbed capacitive circuit and application to matrix display screens
US6252566A · kind A · utility
5Cited by
8References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 2, 1998 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Jun 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0209
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A compensation process for a circuit comprising at least one first conductor at a specified potential, at least one second conductor generating disturbances by capacitive coupling to the conductor and at least one disturbance compensation bus capacitively coupled to the first conductor by a first capacitor includes the steps of measuring the voltage and the current on the compensation bus, calculating the voltage on the first disturbed conductor, and determining the set-point voltage to be applied to the compensation bus in order to compensate for the disturbance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.