Multi-generator, partial array Vt tracking system to improve array retention time
US6252806A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2000 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | May 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.