Memory device with reduced power consumption when byte-unit accessed
US6252807A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Dec 9, 1999 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Dec 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is arranged in such a manner that an access-target memory cell is selected from a plurality of memory cells in accordance with the level of the byte-enable signal at the timing when the level of the corresponding row address strobe signal (/RAS signal) changes, and by this arrangement, the problem resided in the conventional memory device that it could not be decided as to whether a memory block in the DRAM core was to be a selected or non-selected byte until the fall of the corresponding column address strobe signal (/CAS signal), and thus the column decoder and the preamplifier that start operating at the fall of the /RAS signal could not be efficiently controlled is solved, and due to this, electric power that might otherwise be consumed at the time of executing a byte-unit access to the wide-bus DRAM can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.